Pentek introduces Jade Model 71481 XMC FPGA module |

Pentek introduces Jade Model 71481 XMC FPGA module

December 282016
Pentek introduces Jade Model 71481 XMC FPGA module

December 28, 2016 - Pentek introduced the Jade Model 71841, a 1-channel, 3.6 GHz 12-bit A/D or 2-channel, 1.8 GHz 12-bit A/D XMC module based on the Xilinx Kintex Ultrascale FPGA.

The Model 71841 comes preconfigured with a suite of built-in functions for data capture, synchronization, time tagging and formatting, making it a turn- key interface for radar, communications or general data acquisition applications. The Model 71841 features an A/D acquisition IP module and a programmable DDC for data capture and moving. Single-channel mode decimation can be programmed to 8, 16 and all values from 32 to 528 in steps of 16. Dual-channel mode decimation can be programmed to 4, 8 and all values from 16 to 256 in steps of 8 with both channels sharing the same decimation rate. In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to the A/D sampling frequency.

The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. A programmable 15-bit gain adjustment allows the Model 71841 to have a full-scale input range of +2 dBm to +4 dBm. A built-in Auto Sync feature supports A/D synchronization across multiple modules.

Evolved from proven designs of the Pentek Cobalt and Onyx architectures, the Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50%.

As the central feature of the Jade architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. Jade supports an optional 5 GB bank of DDR4 SDRAM memory for custom applications. The memory to Gen.3 x8 PCIe link can sustain 6.4 GB/s data transfers, a 20% improvement over the Onyx architecture. Eight additional gigabit serial lanes and LVDS general purpose I/O lines are available for custom solutions.

Pentek’s Navigator Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite providing a plug-and-play solution to the complex task of IP and control software creation and compatibility. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work at the API level for software development and with a graphical interface for IP design.

Pentek’s Navigator FDK provides complete data acquisition and processing IP. When the design is opened in Vivado’s IP Integrator, the developer can access every component of the Pentek design, replacing or modifying blocks as needed for a specific application. All blocks use industry standard AXI4 interfaces providing a well-defined format for custom IP to connect to the rest of the design. In addition to the IP specific to the supported Jade board, Navigator also includes processing blocks for some of the most commonly used algorithms.