- June 27, 2019
June 27, 2019 —Four 20-output differential clock buffers that exceed PCIe Gen 5 jitter standards for data center applications are available from Microchip Technology. The ZL40292 (85Ω termination) and ZL40293 (100Ω termination) are specifically designed to meet the DB2000Q specification while the ZL40294 (85Ω termination) and ZL40295 (100Ω termination) are designed to meet the DB2000QL industry standard. All are i suited for next-generation servers, data centers, storage devices and other PCIe applications.These devices also meet PCIe Gen 1, 2, 3 and 4 specifications.
Each buffer is a complement to chipsets where distributed clocks are required across several peripheral components, such as Central Processing Units (CPUs), Field Programmable Gate Arrays (FPGAs) and Physical layers (PHYs) in data center servers and storage devices, along with many other PCIe applications. The devices’ low additive jitter of approximately 20 femtoseconds (~20 fs) exceeds the DB2000Q/QL specification of 80 femtoseconds (80 fs). These devices will minimize jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.
The buffers use Low-Power High-Speed Current Steering Logic (LP-HCSL). This feature gives customers the ability to drive longer traces on their board, while reducing components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers.
The ZL40292 and ZL40293 are available now for sampling and in volume production in 72-pin 10 x 10 mm QFN packages. The ZL40294 and ZL40295 are available now for sampling in the 80-pin 6 x 6 QFN packages.