- February 28, 2017
March 1 2017 ‚îÄ Pentek introduced the Model 71821 data converter XMC module. The Model 71821 is a three-channel, 200 MHz, 16-bit A/D, with multiband digital down converters (DDCs) and one digital upconverter (DUC) to two 800 MHz 16-bit D/As, XMC module based on the Xilinx Kintex Ultrascale FPGA and can be used in many applications.
The Model 71821 is designed for engineers building a Digital RF Memory (DRFM) application where multi-channel inputs can digitize an incoming RF input signal at bandwidths up to 80 MHz and then generate a processed version of that RF signal as an analog output with very low and deterministic latency.
For DRFM radar applications, an incoming radar pulse is digitized and sent to the FPGA, which can apply a range of DSP algorithms before delivering the modified signal to the D/A for transmission back to the radar to simulate a reflected pulse. These algorithms are intended to confuse, deceive, or disable the radar, depending on mission objectives. Being a coherent representation of the original signal, the transmitting radar will not be able to distinguish it from other legitimate signals it receives and processes as targets. If the signal is stored in memory, it can be used to create false range targets both behind (reactive jamming) and ahead of (predictive jamming) the target intended for protection. Slight modifications in frequency simulate Doppler shifts to create false target velocity. DRFM can also be used to create distorted phase-fronts, which is essential for countering monopulse radar angular measurement techniques.
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer-coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Kintex UltraScale FPGA for signal-processing, data capture and routing to other module resources.
A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages.Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
The Model 71821 features three A/D Acquisition IP modules for easily capturing and moving data. Each IP module can receive data from any of the three A/Ds or a test signal generator. Powerful linked-list DMA engines move the A/D data through the PCIe interface in a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC.