A Safe Passage through the Real-Time Maze

By Frank Iwanitz and Wolfgang Langer, Softing

A Safe Passage through the Real-Time Maze According to the ARC Advisory Group, Industrial Ethernet continues to gain market share for manufacturing networks, with growth coming especially fast at the device level of the network. Industrial Ethernet is migrating downward in the network hierarchy due to its ability to integrate data-intensive devices into the IT infrastructure, enabling use of the data for both control and higher-level supervisory functions. The chart below, taken from a recent ARC report on the topic, shows end-users are rapidly adopting Industrial Ethernet technology, with projected compound growth rates of 30% through 2012.

This trend illustrates the need for device manufacturers to position themselves within this emerging market in order to stay competitive. Today, Ethernet at the physical layer is combined with other more proprietary or specialized Real-Time Ethernet (RTE) protocols (e.g. EtherCAT, EtherNet/IP, PROFINET). The objective is to optimize performance of a particular function or machine, while keeping the advantages of Ethernet's ubiquity and openness. This universal access point can simultaneously serve I/O data communication, parameterization, configuration, diagnosis, and other applications. The ideal Ethernet interface simultaneously supports standard protocols like HTTP and FTP in addition to industry specific RTE-protocols to ensure scalability and flexibility. The main difference between standard and RTE protocols is that RTE protocols have specific requirements when it comes to deterministic communication behavior.

Field device manufacturers are looking for robust, yet economical solutions that facilitate the design of devices with built-in flexibility to support the multitude of communication protocols required in today's automation systems. FPGAs (Field-programmable Gate Arrays) represent an elegant answer to this search. FPGAs combined with Intellectual Property cores (IP cores) for standard Industrial Ethernet and RTE protocols enable designers to implement any of the communication standards on a single board. This, not only, reduces the form factor but saves time. Device manufacturers can add industry-standard networking capabilities to their automation products cost-effectively while retaining FPGA reprogrammable design flexibility in their systems.

The remainder of this document details the design concepts for a flexible industrial Ethernet interface using the Cyclone III FPGA from Altera and demonstrates how such a design can protect your investment by utilizing the built-in flexibility of an FPGA.

Presenting the solution

Today, various communication systems, intended to provide access to real time data over Ethernet, co-exist in the market. Each such system is designed to support a particular set of requirements. The Industrial Ethernet protocols EtherCAT, EtherNet/IP, and PROFINET are the three most significant systems in the industry and have gained wide market acceptance. Device vendors of, for example, sensors and actuators, have to support these protocols to be able to compete successfully in the various industries and markets. Two topics are especially important here:

  • optimal support of the different RTE protocols within a single hardware platform
  • investment protection by designing field-upgradable products to provide for future requirements or standards without the need to change the hardware.

    An FPGA-based board ideally satisfies these requirements. FPGA components are customized to a specific task by loading the device with configuration data; this data is generated by compiling a hardware design with an appropriate FPGA tool. The hardware design is created using a kind of computer-language (VHDL or Verilog) and, to save time, usually includes pre-written blocks (or IP cores) that are licensed from a specialist design company. Examples of IP cores include I/O interfaces (e.g. UARTs or PWM), logic-processing functions (e.g. FFT/FIR filters), or more complex design blocks like memory controllers or even soft microprocessors like Altera's Nios II (a high-performance 32-but RISC CPU). For Industrial Ethernet applications IP cores for various RTE protocols are available.

    During the hardware design process it is determined what kind of IP cores are needed, how they interface with peripherals like external memory, and how to interconnect the individual IP cores. The resulting design of the internal workings of the FPGA is stored in a non-volatile memory component and serves as a blueprint for initializing the FPGA design during start-up. This means that design upgrades, due to changing requirements or evolving specifications, do not require re-designs of the device hardware but are simply achieved by generating a new blueprint configuration for the FPGA and loading it into the memory. An additional benefit is the fact that your hardware design does not depend on proprietary (and sometimes expensive) ASICs, but is based on an economical, readily available, and versatile high-volume FPGA that has been configured (programmed) for a specific application.

    Figure 1 shows the block diagram of an Altera Cyclone III FPGA (with 40 k logic elements) that supports various RTE protocols. The design contains one IP core for RTE hardware support. The diagram includes an Ethernet switch with two external and one internal port that enables RTE devices to operate in a daisy-chain topology. The internal port is used to exchange data between a logical MAC-port on Nios II soft-core CPU and the switch component using a FIFO buffer. In addition to the switch core, this particular design includes the following IP cores: Nios II soft-core CPU (running the protocol stack), a DP-RAM core, a memory interface core, and additional cores. The second Nios II CPU is optional and could run the application program.

    Figure 1: IP Core design to optimally support RTE protocols

    It is vital to match a high-quality hardware design with a high-performing operating system otherwise the software will limit your system performance. A designer can choose from a number of sophisticated operating systems for the Nios II processor. For this discussion, C-Linux and eCos represent the most relevant choices. Both are free-of-charge and come with a big support community. ECos, although a light-weight operating system, includes support for all essential IP applications (e.g. SNMP). C-Linux, on the other hand, offers native support for a wide range of applications and protocols of which security is only one example. On the downside, C-Linux requires significantly more resources.

    Today, Softing offers the following RTE protocols for eCos: PROFINET IO as Device according to Conformance Class B and EtherNet/IP as Adapter. At the time this article was written, the EtherCAT as Slave functionality was still under development. The single Ethernet interface used by the according RTE IP-cores is complemented by a single API for all protocols. Softing's Simple Device Application Interface (SDAI) is an extremely efficient protocol abstraction layer that offers a single application interface for all RTE protocols - this significantly speeds-up device integration and time-to-market while at the same time simplifies support and maintenance.

    Examples of how to integrate RTE technology into field devices

    Integration model 1: Hardware designed by device manufacturer
    In this model, the device manufacturer develops the hardware based on the Altera Cyclone III FPGA. This approach is especially effective, if the device application requires the integration of additional IP cores that contain vendor specific technology, e.g. for drive control etc. An evaluation-kit such as the MercuryCode board from EBV is an ideal starting point for evaluating FPGA technology. The kit consists of an evaluation board and the necessary development environments for both hardware and software. All aforementioned operating systems and RTE stacks run on the MercuryCode evaluation platform and all required IP cores are commercially available. The evaluation-kit is ideal to verify the interoperability of the design with other devices. In addition, the kit may be used for prototype integration into a target device. After a successful evaluation, the hardware and software development task will follow. The overall process is shown in figure 2. Typically, vendor-specific IP cores in conjunction with IP cores from Altera and RTE IP cores from Softing will be used for the development.

    Figure 2: Development process during FPGA integration

    Integration model 2: Use of Softing's Real-Time Ethernet Module
    Softing's Real-Time Ethernet communication module, shown in figure 3, is a complete board-level solution that is an excellent alternative for use in low-volume products or when a device manufacturer does not have the necessary R&D bandwidth to design a demanding RT Ethernet interface.

    Softing offers an appropriate integration package in case there is no need for a vendor specific FPGA design. This means that the device manufacturer has access to an off-the-shelf Real-Time Ethernet Module with installed hardware-configuration, protocol software, and operating system.

    Figure 3: FPGA-RTEM - Real-Time Ethernet communication module based on Altera's Cyclone III FPGA

    The communication module is delivered with a full development environment required to develop device specific application routines necessary for seamless device integration.

    A device vendor has two main options for the physical device integration:
    A. direct integration of the RTEM as supplied,
    B. Softing performs a re-design of the communication module based on specified requirements (different form factor, etc.)

    The table below illustrates design activities by the device vendor and Softing depending on the selected integration model. 


    Two solutions on a single hardware platform RTE and Standard-application using the same interface

    The tremendous flexibility of Softing¡¦s communications module is demonstrated by the ability to run standard applications using TCP/IP at the same time as various RTE protocols. In order to achieve this task, a developer has the option to simply add another Nios II processor that executes, for example, C-Linux operating system. C-Linux basically offers native support for all standard communication protocols. Furthermore, using a second Nios II processor offers a clean separation between the communication channels for RTE and standard TCP/IP protocols as shown in figure 4.

    Figure 4: IP core structure supporting both RTE and standard TCP/IP

    This design incorporates a switch component with two internal ports, each having an individual Ethernet address. As a result, a product developer can design a field device that offers two IP addresses to permit the independent and simultaneous support of, for example, a remote maintenance application and a real-time control application.

    Advantages of using FPGA at a glance

    An FPGA is a semiconductor device containing programmable logic components called "logic blocks," and programmable interconnects. When you program or configure the FPGA you set the logic blocks and interconnects in such a way that the FPGA delivers the functionality of a compiled hardware design. To change the functionality of the FPGA all you need to do is program a different configuration making it easy to deliver product updates or different feature sets. The creation of FPGA configurations is greatly accelerated by the use of pre-built IP cores for complex or custom features. IP cores are easily re-used between different designs, different size FPGA devices and even to new generations of FPGA device.

    The logic capacity of an FPGA can be defined by the number of logic elements (LE) it contains. The number and size (in LE) of IP cores used for a specific application dictates the size of the FPGA needed. Cyclone III devices are manufactured in pin compatible packages with different logic capacities sizes, so, for example, you could upgrade a system with a 25 KLE FPGA to a 40KLE device without changing the design of your board. This means that you can easily add more features (e.g. more Nios II processors) into the FPGA when required. This demonstrates one of the most important advantages of FPGAs - their flexibility.

    Mass production and continuous improvements in the production process take FPGAs into the same price range as ASICs. The major difference between an ASIC and an FPGA is that an FPGA is less subject to obsolescence. At the same time, an FPGA does not consume a lot of power. For example, a Cyclone III configuration as shown in figure 4 consumes only 600 mW.

    The availability of excellent development environments and first-class operating systems set today's FPGAs at par with micro processors. This high-performance is demonstrated with Softing's PROFINET IO protocol IP core that is able to achieve cycle times easily approaching 1 ms. This means that for applications like Industrial Ethernet interfaces that require built-in flexibility, FPGAs can offer exactly what is necessary without any additional overhead in cost, performance or development time.

    Frank Iwanitz - Wolfgang Langer
    Softing AG - Softing North America, Inc.