Microchip Technology announces dsPIC33CH512MP508 dual-core & dsPIC33CK64MP105 single-core Digital Signal Controllers (DSCs) | Automation.com

Microchip Technology announces dsPIC33CH512MP508 dual-core & dsPIC33CK64MP105 single-core Digital Signal Controllers (DSCs)

Microchip Technology announces dsPIC33CH512MP508 dual-core & dsPIC33CK64MP105 single-core Digital Signal Controllers (DSCs)

March 13, 2019 — Microchip Technology announced dual- and single-core dsPIC33C Digital Signal Controllers (DSCs) with more options to meet changing application requirements across memory, temperature and functional safety.

Microchip’s dsPIC33CH512MP508 dual-core DSC enables support for applications with larger program memory requirements. The dsPIC33CK64MP105 single-core DSC adds a cost-optimized version for applications that require smaller memory and footprint. Developers can scale across product lines using the new devices, which are pin-to-pin compatible within the dsPIC33CH and dsPIC33CK families.

The dsPIC33CH512MP508 (MP5) family expands the dsPIC33CH with Flash memory growing from 128 KB to 512 KB and triples the program RAM from 24 KB to 72 KB. This enables support for larger applications with multiple software stacks or larger program memory, such as automotive and wireless charging applications. More memory is needed to accommodate AUTOSAR software, MCAL drivers and CAN FD peripherals in automotive applications. Implementing wireless charging in automotive applications requires additional software stacks for the Qi protocol and Near-Field Communication (NFC), driving the need for even more program memory. Using Live Update capability for real-time firmware updates is essential for high-availability systems but also doubles the overall memory requirement. In the dual-core devices, one core can function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions. For example, having two cores facilitates partitioning of the software stacks for parallel execution of the Qi protocol and other functions such as NFC to optimize performance in automotive wireless charging applications.

The dsPIC33CK64MP105 (MP1) family extends the recently introduced dsPIC33CK family with a cost-optimized version for smaller memory and footprint applications, offering up to 64 KB Flash memory and 28- to 48- pin packages. Package sizes are available as small as 4 mm x 4 mm. This device offers a combination of features for automotive sensors, motor control, high-density DC-DC applications or stand-alone Qi transmitters. Both single- and dual-core dsPIC33C devices enable deterministic performance for time-critical control applications, providing expanded context selected registers.

All devices in the dsPIC33C family include a fully featured set of functional safety hardware for ASIL-B and ASIL-C certifications in safety-critical applications. Functional safety features include multiple redundant clock sources, Fail Safe Clock Monitor (FSCM), IO ports read-back, Flash Error Correction Code (ECC), RAM Built-In Self-Test (BIST), write protection, analog peripheral redundancies and more. A set of CAN-FD peripherals, along with the support for 150°C operation, make these devices suited for use in extreme operating conditions such as under-the-hood automotive applications.

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