Abaco Systems introduces MMS8010 Micro Mezzanine System (MMS) 3U VPX carrier card and MMS6245 XMC carrier card | Automation.com

Abaco Systems introduces MMS8010 Micro Mezzanine System (MMS) 3U VPX carrier card and MMS6245 XMC carrier card

Abaco Systems introduces MMS8010 Micro Mezzanine System (MMS) 3U VPX carrier card and MMS6245 XMC carrier card

May 31, 2017 Abaco Systems introduced the MMS8010 Micro Mezzanine System (MMS) 3U VPX carrier card and MMS6245 XMC carrier card. They are designed to enable customers to achieve flexibility in configuring the broad range of mixed signal I/O typically required by today’s advanced embedded systems while minimizing chassis slot occupancy.

Abaco’s patented MMS system can deliver a range of serial protocols, digital I/O, audio and analog interfaces via a choice of Electrical Conversion Modules (ECMs). Up to six ECMs can be mounted on the MMS8010 3U VPX carrier, while the MMS6245 XMC can host up to four ECMs. ECMs can also be mounted on PMCs, such as the MMS5918.

A typically challenging application requirement such as a modern radar DSP subsystem, with its requirement for the analog and FPGA technology, may also require mixed I/O functions such as four serial channels, two analog measurement channels and 16 digital channels. Prior to the launch of the MMS8010 and MMS6245, this would have required either several cards to be configured, using precious chassis slots, or a custom solution to be developed.

The MMS8010 is offered in both a VITA 48.1 air-cooled configuration as well as a VITA 48.2 conduction cooled configuration, allowing customers to move from development to deployment with a common set of hardware. The MMS6245 is available as a convection cooled solution.

The MMS8010 is VITA 65 compliant and maps the 96 user-configurable pins to VPX backplane signals.  The MMS6245 is VITA 42.3 compliant and maps the 64 user-configurable pins to the front panel via a 68-pin SCSI style connector. Both come pre-loaded with a default FPGA image compiled in Quartus Prime from Altera with Qsys providing the interconnection between the Avalon bus IP components within the FPGA. The FPGA is effectively the engine for the carrier, orchestrating processing and I/O functions for the installed ECMs. 

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