ams introduces A30 analog CMOS process

December 6, 2016 -- ams AG announced the availability of Analog CMOS process (“A30”). The A30 process provides noise performance and is realized as an optical shrink by a factor of 0.9 from ams’ 0.35µm High-Voltage CMOS process family.

The A30 technology features isolated 3.3V devices (NMOSI and PMOSI), isolated 3.3V low Vt devices (NMOSIL and PMOSIL), an isolated high voltage device with thin gate oxide (NMOSI20T), vertical bipolar transistors (VERTN1 and VERTPH) as well as an isolated 3.3V super-low noise transistor (NMOSISLN), which offers flicker noise on the level of 0.46 pA/Hz (@1kHz, Ids=1µA @Vds=3V, 10x1.2µm²). It enables flicker noise reduction by at least a factor of 4 to 10 for high drain currents compared to H35 process. Passive devices such as various capacitors (poly, sandwich and MOS varactor) and resistors (diffusion, well based, poly, high resistive poly and precision) complete the device offering.

The A30 process is ideally suited for ultra-low noise sensing applications and analog read-out ICs which require noise optimized input stages or high signal-to-noise ratios. It allows the development of innovative solutions for consumer electronics, automotive, medical and IoT devices. The A30 process is manufactured in ams’ 200mm fabrication facility ensuring low defect densities and high yield. All 0.30µm elements are drawn and verified as 0.35µm devices. The optical shrink (factor of 0.9) is done in the mask shop on the completed GDSII data and results in smaller die sizes respectively more dies per wafer.

The A30 process is supported by the hitkit, ams’ process design kit. Based on Virtuoso Custom IC technology 6.1.6 from Cadence®, the new hitkit helps design teams to significantly reduce time-to-market for highly competitive products in the analog-intensive mixed-signal arena. Offering highly accurate simulation models, extraction and verification run sets for both Calibre and Assura and flexible SKILL-based PCells, the new hitkit provides a comprehensive design environment and a proven route to silicon.