April 4, 2011 - Altera announced a HD WDR video surveillance chipset. The chipset combines an Altera Cyclone IV E FPGA with a security chip that supports Apical’s HD WDR full image signal processing (ISP) pipeline IP and AltaSens’ 1080p60 A3372E3-4T image sensor. The chipset simplifies the development of a video surveillance camera system by providing a single vendor source for the IP and the FPGA. Customers won’t have to purchase the IP from a separate vendor and pay extra licensing fees, NRE charges or royalties. Before purchasing the HD WDR video surveillance chipset, customers can download the evaluation IP, Apical’s Image Signal Processing Evaluation Design, directly from Altera’s website, as well as register for an evaluation license online and evaluate the system.
After evaluation, customers can download the Image Signal Processing IP core license online from Altera, and incorporate the IP into their FPGA design in the Quartus II software. This ready-made, yet programmable chipset decreases development time and adds flexibility to the camera design. Leveraging the FPGA’s flexibility, our customers can customize the device with their own specific features, allowing them to further differentiate their products from those of their competitors. Apical’s HD HDR full image signal pipeline IP is optimized to take advantage of the capabilities of the Altera FPGA. No other application specific standard product (ASSP) or DSP platform offers a comprehensive pipeline that incorporates WDR technology using a 1080p60 sensor and datapath.
FPGAs are the only devices that can handle the high bandwidth of data from 1080p and 720p HDR CMOS sensors (for instance, a full HD raster is 2200x1125 pixels x 16+ bits per pixel x 60 frames per second, resulting in >2 Gbps bandwidth). Altera's Cyclone series FPGAs deliver the bandwidth and processing performance needed.
