November 18, 2019 ─ Pentek introduced the Model 54141A, a dual channel analog-to-digital and digital-to-analog converter with sample rates up to 6.4 GHz. Programmable DDCs (digital downconverters) and DUCs (digital upconverters) support connections to IF or RF signals.
The Model 54141A complies with the VITA 65.0 3U VPX specification, it also offers analog and digital interface options for the VPX P2 backplane connector to meet system-specific requirements. In addition to its PCIe Gen.3x8 interface on the VPX P1 connector, it is possible to add up to 8 more gigabit serial lanes connected directly to the FPGA for supporting user-installed protocols.
The Model 54141A supports the emerging VITA 66.5 optical interconnect standard by providing four optical duplex lanes to a mating spring-loaded backplane connector. With the installation of a serial protocol like 10 or 40 Gigabit Ethernet in the FPGA, the interface enables digital communications between boards or chassis independent of the PCIe interface.
The board can be optioned to support VITA 67.3C. This provides analog signal routing through the VPX backplane to replace front panel connectors for RF In/Out, Sample/Reference clocks and Gate/Trigger/Sync/PPS signals.
The Model 54141A uses the Texas Instruments ADC12DJ3200 12-bit A/D converter with an input bandwidth of 6 GHz, which operates in single-channel interleaved mode with a sampling rate of 6.4 GHz or in dual-channel mode with a sampling rate of 3.2 GHz.
A Texas Instruments DAC38RF82 D/A with DUC accepts a baseband real or complex data stream from the FPGA and delivers it to the interpolation, upconversion and dual D/A stages for output signals up to 4 GHz. The two 6.4 GHz 14-bit D/As pair well with the dual input channels while delivering more than twice the output performance of previous generations of Pentek products.
The Model 54141A factory-installed functions include two A/D acquisition modules and a D/A waveform generation IP module. In addition, IP modules for DDR4 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe Gen.3x8 interface complete the factory-installed functions. An optional VITA 49.2 data transport protocol IP module conveys digitized signal metadata for signal acquisition and processing elements in communication, radar or storage systems.
