June 6, 2014 - The RazerCam by EVT is a fast smart camera with free programmable FPGA, which allows data to be preprocessed in real time. Due to the fact that most of the FPGA are available for the user, even complex applications such as contour matching can be processed directly. Based on the XILINX ZYNQ SoC, the camera is equipped with two ARM Cores. The RazerCam series is available in three sensor options, which cover most of the requirements in the machine vision sector. The user can choose between two matrix sensors with 0,4 MP and 3 MP and one line scan sensor with 4k.
The camera is equipped with a LINUX operating system. The user can therefore start programming immediately with the standard tools for LINUX. An extensive API makes it easier to create individual programs in C++ or C code. Thanks to numerous libraries for the ARM processor cores, applications can be solved quite fast. As the FPGA allows the processing of image data already during the image capture, the RazerCam is suitable especially for highspeed tasks, where the data has to be preprocessed.
The programming of the FPGA is possible via various tools. On the one hand with VHDL and on the other hand quite easily with a graphical GUI, where ready-made functional blocks are arranged and compiled. A tool chain, which allows the immediate programming in C/C++, is included and pre-configured. Optionally a directly executable Image for a virtual machine is also included. The programming systems are available for Windows and LINUX programming environments, for native as well as virtual machines.
The system is equipped with an Ethernet interface as well as the CAN Bus or RS485 interface and digital I/Os. Therefore the camera can be embedded directly into process environments. The RazerCam is also available as EyeCheck 4xxx with integrated EyeVision software. As already known from other EyeVision systems, the inspection programs of the EyeCheck 4xxx can be created within the graphical user interface via drag-and-drop programming. Optionally the programming of the FPGA can be done via graphical tools.
